Epcs Serial Flash Controller Qsys
- Epcs Serial Flash Controller Qsys Driver
- Epcs Serial Flash Controller Qsys Manual
- Epcs Serial Flash Controller Qsys
EPCS/EPCQ for the Nios II ecosystem. From EPCS/Q Add S/Labs' Security IP in Qsys. The above project employs Altera’s Serial Flash Controller IP. Be sure to read the readme.txt file. The above project is based on the second boot method described in Altera’s. Set the Avalon slave (iavs0) Base address on S/Labs' Secure Offchip Flash IP to 0x01000000 10.Set the Avalon slave (avlmem) Base address on Intel's Serial Flash controller IP to 0x0 11. Save your Qsys project. 12.In the Qsys window, click on the Generate HDL button. 13.In the Quartus Prime window, run the Compile Design task.
The following table defines the acronyms in this application note: Table 1. AN 736 Acronym Definitions Acronym Description ACDS Altera ® Complete Design Suite API Application Programming Interface CFI Compact Flash Interface EPCQ Altera ® Quad SPI flash device HAL Hardware Abstraction Layer HEX Hexadecimal file: this is an ASCII text file with the extension of.hex. It stores the initial memory values for a memory block. I/O Input/Output Memcpy Memory copy OCRAM On-chip RAM RAM Random Access Memory SBT Software Build Tools SoC System on a Chip SOF SRAM Object Files UFM User Flash Memory XiP Execute in Place Description of the Altera Serial Flash Controller. The Altera ® Serial Flash Controller with Avalon interface allows Nios ® II processor systems to access Altera ® EPCQ flash memory, which supports standard, quad and single- or dual-I/O mode. The Nios ® II processor SBT supports the Nios ® II booting from the Altera ® Serial Flash Controller. In addition, a Nios ® II hardware abstraction layer (HAL) driver is available for the Altera ® Serial Flash Controller that allows an application to read, write, or erase flash.
Scenarios for Booting Nios II from EPCQ Flash. The Nios ® II processor supports the following two boot options using EPCQ flash:. The Nios ® II processor application executes in place from EPCQ flash. The Nios ® II processor application is copied from EPCQ flash to RAM using a boot copier. Summary of Nios II Processor Boot Options Using EPCQ Flash Boot Option Application Code Stored Location Application Run-time Location Method Nios ® II processor application executes in place from EPCQ flash EPCQ EPCQ (XIP) + OCRAM (for writable data sections) Using altload function Nios ® II processor application is copied from EPCQ flash to RAM using boot copier EPCQ OCRAM/ External RAM Using a memcpy-based boot copier. The execute-in-place option is suitable for Nios ® II processor applications which require limited on-chip memory usage.
Epcs Serial Flash Controller Qsys Driver
The altload function operates as a mini boot copier which initializes and copies only the writable memory sections to on-chip RAM (OCRAM). The code section (.text), which is a read-only section, remains in the Altera ® EPCQ flash memory region. Retaining the read-only section in EPCQ helps to minimize RAM use, but may limit the code execution performance. The Nios ® II processor application is programmed into the EPCQ flash.
Epcs Serial Flash Controller Qsys Manual
The Nios ® II processor reset vector points to the EPCQ flash to allow code execution after the system resets. If you are debugging the application using the source-level debugger, you must use a hardware breakpoint because the EPCQ cannot efficiently support random memory access. Nios II Processor Application Copied from EPCQ Flash to RAM. You can use a boot copier to copy the Nios ® II application from EPCQ flash to RAM when multiple iterations of application software development and high system performance are required. Altera ® recommends this solution for Nios ® II processor booting from Altera ® Serial flash (EPCQ). The Nios ® II SBT tool automatically adds the Nios ® II processor memcpy-based boot copier to the system when the executable file (.elf) is converted to the memory initialization file (.hex). The boot copier is located at the base address of the HEX data, followed by the application.
For this boot option, the Nios ® II processor starts executing the boot copier software upon system reset which copies the application from the EPCQ to the internal or external RAM. Once this completes, the Nios ® II processor transfers the program control over to the application.
Note: Your.sof image size influences your reset vector offset configuration. The reset vector offset is the start address of the.hex file in EPCQ flash and it must point to a location after the.sof image. You can determine the minimum reset vector offset by using the following equation: minimum reset vector offset= (.sof image start address +.sof image size) in HEX For example, if your.sof image starts at address 0x0 and is 512 KB in size, then the minimum reset vector offset location you can select is 0x0080000. If the.sof image space and the reset vector offset location overlap, Quartus ® Prime software displays an overlap error. Under Exception Vector, you may select EPCQ ( epcqcontroller0.avlmem) or OCRAM in the Exception vector memory drop-down menu. In this example, 0x20 is listed for the Exception vector offset entry. Note: When executing-in-place, the Nios ® II processor boots and runs directly from EPCQ flash, without copying any code at boot time.
Because the Nios ® II begins executing at the reset address in this case, exception vectors must be located at a nonzero exception vector offset to allow for instructions between the reset vector and the base of the exception vectors. Thus, you must include an exception vector offset when the reset vector and the exception vector point to the same memory and no boot copier is present.
Click Finish. You will return to the Qsys System Contents tab.
Double-click on the Altera Serial Flash Controller IP to open the Altera Serial Flash Controller Parameter editor. Select the Configuration device type based on your hardware design and choose the desired I/O mode. Close the Parameter Editor and return to the Qsys System Contents tab.
Click Generate HDL to generate your Qsys design. Compile your design in Quartus ® Prime software. Reset and Exception Vector Settings for Nios II Boot Copier Method. Note: Your.sof image size influences your reset vector offset configuration. The reset vector offset is the start address of the.hex file in EPCQ flash and it must point to a location after the.sof image. You can determine the minimum reset vector offset by using the following equation: minimum reset vector offset= (.sof image start address +.sof image size) in HEX For example, if your.sof image starts at address 0x0 and is 512 KB in size, then the minimum reset vector offset location you can select is 0x0080000.
If the.sof image space and the reset vector offset location overlap, Quartus ® Prime software displays an overlap error. Under Exception Vector, select OCRAM/External RAM in the Exception vector memory drop-down menu. In this example, 0x20 is listed for the Exception vector offset entry. Click Finish. You will return to the Qsys System Contents tab.
Double-click on the Altera Serial Flash Controller IP to open the Altera Serial Flash Controller Parameter editor. Select the Configuration device type based on your hardware design and choose the desired I/O mode. Close the Parameter Editor and return to the Qsys System Contents tab.
Click Generate HDL to generate your Qsys design. Compile your design in the Quartus ® Prime software.
Epcs Serial Flash Controller Qsys
BSP Editor Settings. In the Nios ® II SBT window, select File Nios II Application to create a new application. Develop your Nios ® II application. Alternatively, you can use a template for the application creation.
Point your application to the BSP location that you have created in the previous section. Once the application development finishes, right-click on the project in Project Explorer and select Build Project.
A.elf file is create under the project folder. Next, generate the HEX file using the meminitgenerate utility. Right-click on the project in Project Explorer and select Make Targets Build. The Make Targets window opens as shown below. In the Quartus ® Prime software, go to File Convert Programming Files to open the Convert Programming File tool. Under Output programming file section, set the following items:. Programming file type: JTAG Indirect Configuration File (.jic).
Configuration device: Select according to your EPCQ type. Mode: Active Serial. File name: You may select your preferred path for the output file (.jic). By default this is generated under your project root directory. Keep the default settings for Create Memory Map File and Create config data RPD.
Under Input files to convert section:. Select Flash Loader, then Add Device to select the FPGA device that you are using. Click OK when you are done.
Select SOF Data, then Add File to choose the.sof file generated by Quartus II compilation. Click on the.sof file that you have just added. Next, select Properties and enable Compression. Click on SOF Data and select Properties. The SOF Data Properties window opens. Under Address mode for selected pages, select Start and set the start address (32-bit hexadecimal).
If using a Cyclone ® V SoC development board, set the start address to 0x0 to avoid a 'size exceeds memory capacity' error. The Nios ® II processor memcpy-based boot copier has the following features:. Supports EPCQ, CFI and Altera ® on-chip flash (UFM) flash memories. Can locate software application in flash. Unpacks and copies software application image to Random Access Memory (RAM). Automatically switches to application code in RAM after copy completes The Nios ® II processor boot copier is used when the Nios ® II soft processor application is copied from EPCQ flash to RAM. The memcpy-based boot copier is automatically appended to the.hex file by the Nios ® II SBT tool when the executable file (.elf) is converted to a memory initialization file (.hex) using the make meminitgenerate target.
This operation takes place whenever the.text linker section is located in a different memory than where the reset vector points, which indicates a code copy is required. The function of the boot copier is to copy the software application to your desired location such as RAM. Once the copy is complete, the boot copier passes the system control to the application.